PLA's are widely used in digital systems to provide fixed logic functions at relatively low cost. For instance, a PLA may be fabricated as a portion of a larger circuit to provide certain logic functions.
A two level PLA comprises, in addition to various control and other functions, two separate logic arrays. For instance, a first logic array may comprise an array of AND functions (which may or may not be actually implemented with AND gates) and a second logic array may comprise an array of OR functions. As is familiar in the art, one "programs" such a device by means of choosing the interconnections between the various functions.
In a typical two-level PLA, logical inputs are first provided to the AND array (also referred to as the product section because of the identity between the Boolean AND and the logical product functions). The outputs of the product section are provided to the OR array (also referred to as the sum section). The outputs of the sum section are taken as the outputs of the PLA.
Access to such a two-level PLA requires several steps. First, the inputs on the data must be latched for input to the product section. Next, the product section must be instructed to process those inputs, commonly referred to as discharging the product section. Next, the sum section must be similarly discharged to process the outputs of the product section. Finally, a signal must be generated indicating that the outputs of the PLA are now valid data.
In a system in which access to the PLA is a critical factor in the performance of the system, two parameters describing access to the PLA are useful. First, it is desirable that the time between the requested access to the PLA and the output of valid data be as small as possible. This parameter will be referred to as access time and will be more rigorously defined hereinbelow. In addition, in a system in which the inputs to the PLA may be changing rapidly, it is desirable that the outputs reflect as recent a state of the inputs as possible. This parameter will be referred to as the age of the response and will be more rigorously defined below.
For purposes of clarity, several definitions will be helpful. When a signal is said to be asserted, it shall be deemed to mean that the signal is made to be active, whether this implies that it is high or low. When a signal is said to be negated, this shall be deemed to mean that the signal is made inactive, whether this implies that it is high or low.